Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Solving Satisfiability Problems on FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Partitioning Methods for Satisfiability Testing on Large Formulas
CADE-13 Proceedings of the 13th International Conference on Automated Deduction: Automated Deduction
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
A hardware relaxation paradigm for solving NP-hard problems
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
| Hi-index | 0.00 |
Satisfiability (SAT) is a computationally expensive algorithm central to computer science. In this paper, we present a virtual logic algorithm that allows an FPGA based reconfigurable computing platform to process SAT solver circuits much larger than its available capacity. Our algorithm is based on decomposition techniques that create independent sub-problems (pages) that fit the size of the available reconfigurable hardware. Those pages can take turns reusing the platform, and creating a virtual logic environment.