Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Encoding multi-valued functions for symmetry
Proceedings of the International Conference on Computer-Aided Design
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Algebraic operations were developed for binary logic synthesis and extended later to apply to multi-valued (MV) logic. Operations in the MV domain were considered more complex and slower. This paper shows that the MV algebraic operations are essentially as easy as bunary ones, with only a slight overhead (linear in the size of the expression) in transformation into and out of the binary domain. By introducing co-singleton sets as a new basis, any MV sum-of-products expression can be rewritten and passed to a binary logic synthesizer for fast execution; the optimized results can be directly interpreted in the MV domain. This process, called EBD, reduces MV algebraic operations to binary. A pure MV operation differs mainly from its corresponding EBD one in that the former possesses "semi-algebraic" generality, which has not been implemented for the binary logic. Experiments show that the proposed methods are significantly faster, with little or no loss in quality when run in comparable scripts of sequences of logic synthesis operations.