Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
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Development of analog electronics solutions for space avionics is expensive and time-consuming. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from the benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: first, commercial Field Programmable Analog Arrays (FPAA) have very limited variability in the building block components offered on-chip (practically only one type of operational amplifiers/ comparator per chip); and second, these are only qualified for best case scenarios for military grade (-55oC to +125oC). However, the analog circuitry required for sensing and control impose a larger component variability. Moreover, in order to avoid large overheads in mass, energy and wiring, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, i.e. electronics that maintain correct operation while directly exposed to temperature extremes e.g., on Moon (-180°C to +125°C). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) that was developed at JPL. It overcomes both limitations: a larger variety of analog building block components in the cells of the array and the possibility to operate over a wide range by compensating deviations due to temperature using a built in general purpose genetic algorithm (GA) engine as an IP core.