A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
IEEE Transactions on Computers
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
QUKU: A dual-layer reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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Functional units provide the backbone of any spatial accelerator by providing the computing resources. The desire for having rich and expensive functional units is in tension with producing a regular and energy-efficient computing fabric. This paper explores the design trade-off between complex, universal functional units and simpler, limited functional units. We show that a modest amount of specialization reduces the area-delay-energy product of an optimized architecture to 0.86× a baseline architecture. Furthermore, we provide a design guideline that allows an architect to customize the contents of the computing fabric just by examining the profile of benchmarks within the application domains.