Digital image processing (2nd ed.)
Digital image processing (2nd ed.)
Journal of Systems Architecture: the EUROMICRO Journal
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
IEEE Transactions on Computers
PipeRench implementation of the instruction path coprocessor
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Cache performance for multimedia applications
ICS '01 Proceedings of the 15th international conference on Supercomputing
The Garp Architecture and C Compiler
Computer
The MOLEN rho-mu-Coded Processor
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Reconfigurable Computing: A New Business Model and its Impact on SoC Design
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
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The goal of this work is to explore the architectural behavior of FPGAbased coprocessors that are part of general-purpose computer systems. Our analysis shows maximum performance improvements of up to two orders of magnitude in comparison with current high-performance processors. However, the performance benefits exhibited by reconfigurable coprocessors may be deeply influenced by some design parameters. We have studied the impact of hardware capacity, reconfiguration time, memory organization, and system bus bandwidth on the performance achieved by FPGA-based coprocessors. Our results suggest that an unappropriated bandwidth both for the reconfigurable data-path and host bus can degrade enormously the performance improvement. Since the variation of bus bandwidths encountered in contemporary computer systems is substantial, we found that reconfigurable coprocessors are more efficient when placed as close to the processor as possible without being part of its data-path.