A Novel Predication Scheme for a SIMD System-on-Chip

Authors:
Alexander Paar;Manuel L. Anido;Nader Bagherzadeh
Affiliations:
-;-;-
Venue:
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Year:
2002

Citing 6
Cited 2

BLITZEN: a highly integrated massively parallel machine

Journal of Parallel and Distributed Computing - Massively parallel computation
Autonomous SIMD flexibility in the MP-1 and MP-2

SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Guarded execution and branch prediction in dynamic ILP processors

ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A comparison of full and partial predicated execution support for ILP processors

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
Parallel volume rendering on a single-chip SIMD architecture

PVG '01 Proceedings of the IEEE 2001 symposium on parallel and large-data visualization and graphics

A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluator-executor transformation for efficient pipelining of loops with conditionals

ACM Transactions on Architecture and Code Optimization (TACO)

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a novel predication scheme that was applied to a SIMD system-on-chip. This approach was devised by improving and combining the unrestricted predication model and the guarded execution model. It is shown that significant execution autonomy is added to the SIMD processing elements and that the code size is reduced considerably. Finally, the implemented predication scheme is compared with predication schemes of general purpose processors, and it is shown that it enables more efficient if-conversion compilations than previous architectures.