Parallel volume rendering on a single-chip SIMD architecture

  • Authors:

  • M. Meißner;S. Grimm;W. Straßer;J. Packer;D. Latimer

  • Affiliations:

  • University of Tübingen, Auf der Morgenstelle 10/C9, D-72076 Tübingen, Germany;University of Tübingen, Auf der Morgenstelle 10/C9, D-72076 Tübingen, Germany;University of Tübingen, Auf der Morgenstelle 10/C9, D-72076 Tübingen, Germany;ClearSpeed Technology Ltd., Wallscourt Farm, Filton Road, Bristol, UK;ClearSpeed Technology Ltd., Wallscourt Farm, Filton Road, Bristol, UK

  • Venue:
  • PVG '01 Proceedings of the IEEE 2001 symposium on parallel and large-data visualization and graphics
  • Year:
  • 2001

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Abstract

Volume rendering has great potential for parallelization due to the tremendous number of computations necessary. Besides the enormous computational power needed, the memory interface is usually of crucial importance and frequently the bottleneck.This paper presents an implementation of a parallel ray casting algorithm for orthogonal projections on a new single-chip SIMD architecture. Concurrent processing of rays is scheduled such that redundant memory accesses of the individual processing elements can be detected by the channel controller. Hence, data can be read efficiently in block-wise manner. For improved image quality, a permutation of the Shear-Warp algorithm with trilinear interpolation is used. The steps of the ray casting algorithm are carefully mapped onto the architecture avoiding expensive floating point operation, giving superior performance over previously reported results. A detailed analysis illustrates the timing of the individual computations and memory accesses, identifying the costliest parts of the implementation.