Mapping method for dynamically reconfigurable architecture

Authors:
Akira Kuroda;Mayuko Koezuka;Hidenori Matsuzaki;Takashi Yoshikawa;Shigehiro Asano
Affiliations:
Corporate R&D Center Toshiba Corporation;Corporate R&D Center Toshiba Corporation;Corporate R&D Center Toshiba Corporation;Corporate R&D Center Toshiba Corporation;Corporate R&D Center Toshiba Corporation
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

Citing 2
Cited 0

MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems

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Abstract

We present a mapping algorithm for our dynamically reconfigurable architecture suitable for stream applications such as H.264. Because our target architecture consists heterogeneously of four different configuration format units, it's difficult to apply the conventional algorithms. We propose a heuristic mapping algorithm enabling the mapping of generic dataflow graph onto this complex hardware automatically. We mapped five main functions of H.264 decoder onto our architecture and compared the results with those of manual mapping performed by an experienced engineer. The results show optimization of three of the five functions is equal to that in the case of the manual mapping.