Energy efficient address assignment through minimized memory row switching
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Mesh Partitioning Approach to Energy Efficient Data Layout
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multimedia applications are characterized by a largenumber of data accesses and complex array index manipulations.The built-in address decoder in the RAM memorymodel commonly used by most memory synthesis tools, unnecessarilyrestricts the freedom of address generator synthesis.Therefore a memory model in which the address decoderis decoupled from the memory cell array is proposed.In order to demonstrate the benefits and limitations of thisalternative memory model, synthesis results for a Shift Registerbased Address Generator that does not require addressdecoding are compared to those for a counter-basedaddress generator that requires address decoding. Resultsshow that delay can be nearly halved at the expense of increasedarea.