Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
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The hierarchical structure of real-life data dominatedapplications limits the exploration space for high level optimisations.This limitation is often overcome by func-tioninlining. However, it increases the basic block codesize, which causes a significant growth of instruction cachemisses and thus performance slow-down. This effect hasbeen confirmed on experiments with our applications. We have developed a novel methodology for selectivefunction inlining steered by cost/gain balance to trade-offpower and performance. Although this results in a speedup, the increase of the instruction cache misses is stillpresent, i.e. the memory power consumption is higher. Thisimplies the possibility of the Pareto-optimal trade-offs betweenmemory power and performance. Our methodologyis demonstrated on an MPEG-4 video decoder.