Post-silicon debugging targeting electrical errors with patchable controllers (abstract only)

Authors:
Masahiro Fujita;Hiroaki Yoshida
Affiliations:
University of Tokyo, Tokyo, Japan;University of Tokyo, Tokyo, Japan
Venue:
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Year:
2012

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Abstract

Due to continuous increase of design complexity in SoC development, the time required for post-silicon verification and debugging keeps increasing especially for electrical errors and subtle corner case bugs, and it is now understood that some sort of programmability in silicon is essential to reduce the time for post-silicon verification and debugging. Although an easiest way to achieve this is to use FPGA for entire circuits, performance especially in terms of power efficiency compared with pure hardwired logic may be significantly inferior. Here, we discuss partial use of such in-field programmability in control parts of circuits for post-silicon debugging processes for electrical errors and corner case logical bugs. Our method deals with RTL designs in FSMD (Finite State Machine with Datapath) by adding partially in-field programmability, called "patch logic", in their control parts. With our patch logic we can dynamically change the behaviors of circuits in such a way to trace state transition sequences as well as values of internal values periodically. Our patch logic can also check if there is any electrical error or not periodically. Assuming that electrical errors occur very infrequently, an error can be detected by comparing the equivalence on the results of duplicated computations. Through experiments we discuss the area, timing, and power overhead due to the patch logic and also show results on electrical error detection with duplicated computations.