Automated datapath synthesis: A compilation approach
Microprocessing and Microprogramming
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Asynchronous scheduling and allocation
Proceedings of the conference on Design, automation and test in Europe
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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A schedule for a sequential finite-state machine defines a distribution of statements on control steps taking into account constraints on time and resources. A net schedule defines both a partial precedence and concurrent execution of the statements under the same constraints. The author introduces a new net scheduling and allocation model, method, and techniques that permit generation of net schedules minimizing either the execution time or resources. The net schedule is a source to synthesize a sequential schedule with chaining, multicycling, and pipelining, or to structure synthesis directly. Experimental results show the net schedule execution time to be more than 20% less than the sequential schedule execution time in the case of variable execution time of statements. The theoretical results are used in VHDL-based high-level synthesis AHILES system.