Constrained software synthesis for embedded applications
Journal of Systems Architecture: the EUROMICRO Journal
Critical Path Profiling of Message Passing and Shared-Memory Programs
IEEE Transactions on Parallel and Distributed Systems
Critical path analysis of TCP transactions
IEEE/ACM Transactions on Networking (TON)
Net Scheduling in High-Level Synthesis
IEEE Design & Test
Techniques for Optimization of Net Algorithms
PARELEC '02 Proceedings of the International Conference on Parallel Computing in Electrical Engineering
Scheduler implementation in MP SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Implementing real-time video decoding on multimedia processors by complexity prediction techniques
IEEE Transactions on Consumer Electronics
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
This paper presents a methodology of parallel implementations design that starts with abstract sequential descriptions of complex systems when no any parallel solutions have been taken and solves dynamically at real input data very complex tasks that are typical for system-level design. Critical path and parallelization potential based profiling of large sequential algorithms on data flow execution graphs is the kernel of methodology that enables to search for optimal (sub-optimal) parallel implementation solutions at very abstract level of design flow. Experimental results obtained on the critical path and parallelization potential based profiling of MPEG4 video codec and subsequent performance analysis of possible parallel implementations prove usefulness and effectiveness of the developed methodology and tool.