Logic and high level synthesis for communication protocols

Authors:
Ricardo N. B. Lima;Emerson Carli;Aloysio C. P. Pedroza;Luci Pirmez;Antônio C. de Mesquita
Affiliations:
Grupo de Teleinformática e Automação, Universidade Federal do Rio de Janeiro, Rio de Janeiro, RJ, Brasil and COPPE, EE, Programa de Engenharia Elétrica, Departamento de Eletr&# ...;Grupo de Teleinformática e Automação, Universidade Federal do Rio de Janeiro, Rio de Janeiro, RJ, Brasil and COPPE, EE, Programa de Engenharia Elétrica, Departamento de Eletr&# ...;Grupo de Teleinformática e Automação, Universidade Federal do Rio de Janeiro, Rio de Janeiro, RJ, Brasil and COPPE, EE, Programa de Engenharia Elétrica, Departamento de Eletr&# ...;COPPE, EE, Programa de Engenharia Elétrica, Departamento de Eletrônica, Rio de Janeiro, RJ, Brasil;COPPE, EE, Programa de Engenharia Elétrica, Departamento de Eletrônica, Rio de Janeiro, RJ, Brasil
Venue:
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Year:
1999

Citing 2
Cited 0

High-level synthesis: introduction to chip and system design

High-level synthesis: introduction to chip and system design
Analysis of different protocol description styles in VHDL for high-level synthesis

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

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Abstract

This work presents the results obtained using a methodology that allows the hardware implementation and the rapid prototyping of communication protocols through Logic and High Level Synthesis. The implementation results of different description styles of protocols and a comparison among the protocol implementation using the High Level Synthesis technique with standard cells library and the implementation using Programmable Logic Device (PLD) are presented. The results include area analysis and clock frequency evaluation of synthesized hardware.