Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Software pipelining: an evaluation of enhanced pipelining
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Dynamic List-Scheduling with Finite Resources
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
PARSA: A Parallel Program Scheduling and Assessment Environment
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 02
A Comparison of Multiprocessor Scheduling Heuristics
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 02
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Computation intensive DSP applications usually requireparallel/pipelined processors in order to meet specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficientloop scheduling algorithm that reduces data hazards for such DSPapplications. This algorithm has been embedded in a tool, called SHARP,which schedules a pipelined data flow graph to multiple pipelined unitswhile hiding the underlying data hazards and minimizing the execution time.This paper reports significant improvement for some well-known benchmarksshowing the efficiency of the scheduling algorithm and the flexibility ofthe simulation tool.