An SPU reference model for simulation, random test generation and verification

Authors:
Yukio Watanabe;Balazs Sallay;Brad Michael;Daniel Brokenshire;Gavin Meil;Hazim Shafi;Daisuke Hiraoka
Affiliations:
Toshiba Corporation, Horikawa-Cho, Saiwai-Ku, Kawasaki, Japan;IBM, Austin, TX;IBM, Austin, TX;IBM, Austin, TX;IBM, Austin, TX;IBM, Austin, TX;Sony Computer Entertainment Inc., Minami-Aoyama, Minato-ku, Tokyo, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [1][2]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.