Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
The IEC/IEEE Train Communication Network
IEEE Micro
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In this paper a behavioral model of the gateway for the Train Communication Network (TCN) is presented. It has been used in a specific verification tool for TCN devices based on a commercial VHDL simulator. By means of bit level exhaustive simulation in this tool, electronic designs in VHDL language have been validated before prototypes are produced. In this way, a virtual communication network is composed of various TCN device models which interchange pieces of information. These data and the network management parameters have been written in the configuration files of every model through the user interface. Such virtual nodes generate VHDL signals that simulate real traffic of Master and Slave Frames. However, the whole description has not been edited in plain VHDL. Upper level functions have been written in C++; these communicate with the bus controller in VHDL by means of the FLI, a special interface for this purpose. In the case of the gateway, the model consists of some blocks which are common to more simple devices, and a specific one: the TCN gateway function. In addition, an application module must have been inserted in order to produce the message traffic.