A simplified domain-testing strategy
ACM Transactions on Software Engineering and Methodology (TOSEM)
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Predicting the Performance of SoC Verification Technologies
VIUF '00 Proceedings of the VHDL International Users Forum Fall Workshop (VIUF'00)
A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Register-transfer-level design verification: coverage and acceleration
Register-transfer-level design verification: coverage and acceleration
Validation of behavioral hardware descriptions
Validation of behavioral hardware descriptions
A Close Look at Domain Testing
IEEE Transactions on Software Engineering
A Domain Strategy for Computer Program Testing
IEEE Transactions on Software Engineering
| Hi-index | 0.00 |
An innovative domain strategy and coverage metric for integrated circuit design validation is proposed. The domain strategy generates test points to examine the borders of a domain to detect whether a design fault has occurred, as either one or more of these borders have shifted or else the corresponding predicate relational operator has changed. The domain coverage metric is applied to measure the completeness and quality of validation approach. The domain strategy and coverage metric have been implemented using VPI (Verilog Procedural interface) and have been applied to validation of industry circuits under design. Our domain coverage tool works smoothly with simulator and vector generator. The results showed that the domain strategy is efficient to generate test points, the domain coverage metric is powerful to find potential boundary faults.