Predicting the Performance of SoC Verification Technologies

  • Authors:
  • Gregory D. Peterson

  • Affiliations:
  • -

  • Venue:
  • VIUF '00 Proceedings of the VHDL International Users Forum Fall Workshop (VIUF'00)
  • Year:
  • 2000

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Abstract

Verification demands for SoC design looms as one of the most significant challenges to designers. With the substantial costs and increasing importance of system verification technologies, determining the best verification strategy is critical to SoC design and business success. This paper focuses on how a designer can apply a model to perform tradeoffs between the different types of emulation, hardware acceleration, and simulation verification tools available. The predictive power of the modeling approach is applied to usage scenarios to determine the most appropriate verification strategy to employ in current or future SoC development efforts.