Architectural Verification of Processors Using Symbolic Instruction Graphs

  • Authors:
  • A. K. Chandra;Vijay S. Iyengar;R. V. Jawalekar;M. P. Mullen;Indira Nair;Barry K. Rosen

  • Affiliations:
  • -;-;-;-;-;-

  • Venue:
  • ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
  • Year:
  • 1994

Quantified Score

Hi-index 0.00

Visualization

Abstract