On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE Transactions on Computers
Effective and Efficient Test Pattern Generation for Small Delay Defect
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Stuck-open and transition fault testing in CMOS complex gates
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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For decades, EDA test generation tools for digital logic have relied on the Stuck-At fault model, despite the fact that process technologies moved forward from TTL (for which the Stuck-At fault model was originally developed) to nanometer-scale CMOS. Under pressure from their customers, especially in quality-sensitive application domains such as automotive, in recent years EDA tools have made great progress in improving their detection capabilities for new defects in advanced process technologies. For this Hot-Topic Session, we invited the three major EDA vendors to present their recent greatest innovations in hiqh-quality automatic test pattern generation, as well as their lead customers to testify of actual production results.