Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Differential fault simulation for sequential circuits
Journal of Electronic Testing: Theory and Applications
Fault simulation for general FCMOS ICs
Journal of Electronic Testing: Theory and Applications
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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This paper introduces a new fault simulation methodology based onsymbolic handling of fault effects. Boolean variables are related tofaulty signals, and fault effects are propagated by computing gateoutput expressions by means of BDDs. The proposed technique canhandle in a single simulation step such faults as resistive bridges,that exhibit a parametric behavior, thus requiring more simulationswith conventional techniques.