Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A language for describing boundary scan devices
Journal of Electronic Testing: Theory and Applications
Boundary Scan with Built-In Self-Test
IEEE Design & Test
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Test Methodology for VLSI Chips on Silicon
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Design-For-Test Techniques Utilized in an Avionics Computer MCM
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
MCM Foundry Test Methodology and Implementation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
IEEE Design & Test
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MCM testing can be challenging enough when the chip, substrate, and MCM design are within the control of the same company. In the foundry environment, however, even more robust strategies must be adopted. In this paper a test methodology will be described which consolidates the various MCM test stages to form a flexible, low-cost, quick turn-around-time test flow.