A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design benchmarking to 7nm with FinFET predictive technology models
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Modeling symmetrical independent gate FinFET using predictive technology model
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Proceedings of the 50th Annual Design Automation Conference
Power benefit study for ultra-high density transistor-level monolithic 3D ICs
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 2014 on International symposium on physical design
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Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.