Synchronous Handshake Circuits

  • Authors:
  • Ad Peeters;Kees van Berkel

  • Affiliations:
  • -;-

  • Venue:
  • ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
  • Year:
  • 2001

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Abstract

We present the synchronous implementation of hand-shake circuits as an extra feature in the otherwise asynchronous design flow based on Tangram. This synchronous option can be used in the mapping onto FPGAs or as a fall-back option to provide a circuit that is easier to test and integrate in a synchronous environment. When single-rail and synchronous realizations of the same handshake circuit are compared, the synchronous versions typically require fewer state-holding elements, occupy less area, have similar performance, but consume significantly more power (in the examples studied up to a factor four). Synchronous handshake circuits provide a means to study clock-gating techniques based on the synthesis starting from a behavioral-level specification. In addition, the study provides hints as to where the asynchronous hand-shake circuits may be optimized further.