Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology

Authors:
Kiran Puttaswamy;Gabriel H. Loh
Affiliations:
Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta
Venue:
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Year:
2006

Citing 0
Cited 7

Thermal analysis of a 3D die-stacked high-performance microprocessor

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic instruction schedulers in a 3-dimensional integration technology

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Die Stacking (3D) Microarchitecture

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A modular 3d processor for flexible product design and technology migration

Proceedings of the 5th conference on Computing frontiers
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Design space exploration for 3-D cache

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout effects in fine grain 3D integrated regular microprocessor blocks

Proceedings of the 48th Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a floorplanning method based on particle swarm optimization (PSO). We adopted the B*-tree floorplan structure to generate an initial stage with overlap free for placement and utilized PSO to find out the potential optimal placement ...