A cycle accurate power estimation tool

Authors:
Rajat Chaudhry;Daniel Stasiak;Stephen Posluszny;Sang Dhong
Affiliations:
IBM Corporation, Austin, TX;IBM Corporation, Austin, TX;IBM Corporation, Austin, TX;IBM Corporation, Austin, TX
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

Citing 2
Cited 1

Power modeling for high-level power estimation

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IEEE Micro

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

IBM Journal of Research and Development

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Abstract

Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designers on the efficiency of the power management logic. In this paper we present the methodology behind a cycle accurate power estimation tool. This tool was used to estimate the power of a first generation CELL Processor. The tool extracts switching and clock activity from RTL simulations and applies them to transistor level macro power models to calculate the power for every cycle of the simulation trace.