Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Proceedings of the 36th annual international symposium on Computer architecture
POWER7 multi-core processor design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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In this paper, we present CacheVisor - a toolset for visualizing the behavior of shared caches in multicore and multithreaded processors. CacheVisor uses the memory access traces generated by the execution-driven processor simulation to graphically depict the cache sharing dynamics among applications that concurrently use the cache. We present the implementation of CacheVisor and describe how it can be used in computer architecture research and education. The public release of CacheVisor is planned in the near future.