SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Proceedings of the 8th ACM International Conference on Computing Frontiers
CacheVisor: a toolset for visualizing shared caches in multicore and multithreaded processors
PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
Switch-based packing technique to reduce traffic and latency in token coherence
Journal of Parallel and Distributed Computing
Extrinsic and intrinsic text cloning
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Reducing L1 caches power by exploiting software semantics
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Virtually split cache: An efficient mechanism to distribute instructions and data
ACM Transactions on Architecture and Code Optimization (TACO)
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POWER series of processors are the building block for IBM's p-Series servers. With its leading edge microarchitecture, technology and efficient implementation, POWER processors are the dominating RISC processor technology today. POWER processors form the building block for IBM's p-Series servers, which have the largest UNIX marketshare. Over the last 20 years, POWER processors have incorporated many technological innovations, often leading the industry with its new technologies. In this talk, we will describe many key architectural, micro-architectural, RAS and power-management features of the POWER7 core for the first time. POWER7 is IBM's first 8-core processor chip, with each core capable of 4-way SMT, fabricated in IBM's 45nm SOI technology with 11 levels of metal. Details of the processor core will be discussed, along with insights, technical issues and challenges related to designing high performance, power-efficient multi-core chips for building balanced servers.