A framework for power estimation and reduction in multi-core architectures using basic block approach

Authors:
M. Rajasekhara Babu;P. Venkata Krishna;M. Khalid
Affiliations:
School of Computing Science and Engineering, VIT University, Vellore-632015, Tamil Nadu, India.;School of Computing Science and Engineering, VIT University, Vellore-632015, Tamil Nadu, India.;School of Computing Science and Engineering, VIT University, Vellore-632015, Tamil Nadu, India
Venue:
International Journal of Communication Networks and Distributed Systems
Year:
2013

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Abstract

In recent scenarios, power consumption is critical for battery operated devices. There are wide varieties of implementations of dynamic voltage scaling (DVS) algorithm to reduce energy or power. This paper presents a framework called PERMA, power estimator and reducer for multi-core architectures. The PERMA estimates power consumption and suggests analytical procedure to reduce power consumption at basic block level rather than at region level using clock cycles of instructions for a particular architecture (x86). PERMA estimates execution time for each basic block for various voltage levels and chooses best out of these. Therefore, PERMA evaluates the extent to which the voltage can be varied for various Basic Blocks to reduce power consumption without degrading execution time. Finally, it is tested for matrix multiplication of various sizes. There is an improvement in the execution time up to 33.43% with PERMA and 21.89% without PERMA.