Instruction packing: Toward fast and energy-efficient instruction scheduling

Authors:
Joseph J. Sharkey;Dmitry V. Ponomarev;Kanad Ghose;Oguz Ergin
Affiliations:
State University of New York at Binghamton, Binghamton, NY;State University of New York at Binghamton, Binghamton, NY;State University of New York at Binghamton, Binghamton, NY;TOBB Economics and Technology University, Ankara, Turkey
Venue:
ACM Transactions on Architecture and Code Optimization (TACO)
Year:
2006

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Abstract

Traditional dynamic scheduler designs use one issue queue entry per instruction, regardless of the actual number of operands actively involved in the wakeup process. We propose Instruction Packing---a novel microarchitectural technique that reduces both delay and power consumption of the issue queue by sharing the associative part of an issue queue entry between two instructions, each with, at most, one nonready register source operand at the time of dispatch. Our results show that this technique results in 40% reduction of the IQ power and 14% reduction in scheduling delay with negligible IPC degradations.