A Novel Low-Cost Approach to MCM Interconnect Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither Scheme
Journal of Electronic Testing: Theory and Applications
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This paper provides a new test technique for detecting defects in Through Silicon Via (TSV) in 3-D ICs and presents a substrate-dependent equivalent electrical model for TSVs. Process-related defects that affect the functional electrical performance of the TSV are identified, and fault models are developed for each individual defect. The fault models are integrated into the equivalent electrical model of the TSV for testing. Our test technique uses an RF carrier signal modulated with a multi-tone signal with added Gaussian white noise to synthesize the test stimulus; the peak-to-average ratio is measured as output response. We find a significant difference in peak-to-average ratio between defect-free and defective TSVs. Our test technique is very sensitive to small defects in these nanostructures, thereby identifying the defects with high accuracy.