Statistical aging analysis with process variation consideration
Proceedings of the International Conference on Computer-Aided Design
Enhancing NBTI recovery in SRAM arrays through recovery boosting
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Journal of Electronic Testing: Theory and Applications
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Editor's note:Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations.—Yu Cao, Arizona State University