Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling

Authors:
Masanori Kurimoto;Hiroaki Suzuki;Rei Akiyama;Tadao Yamanaka;Haruyuki Ohkuma;Hidehiro Takata;Hirofumi Shinohara
Affiliations:
Renesas Technology Corporation, Itami, Hyogo, Japan;Renesas Technology Corporation, Itami, Hyogo, Japan;Renesas Design Corporation, Itami, Hyogo, Japan;Renesas Design Corporation, Itami, Hyogo, Japan;Renesas Design Corporation, Itami, Hyogo, Japan;Renesas Technology Corporation, Itami, Hyogo, Japan;Renesas Technology Corporation, Itami, Hyogo, Japan
Venue:
Proceedings of the 45th annual Design Automation Conference
Year:
2008

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Abstract

Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.