Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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This paper proposes a novel high level synthesis for post-silicon skew adjustable datapaths. Our objective in high level synthesis is to maximize the "skew adjustability", i.e. the probability of the success of skew adjustment under delay variations. Skew adjustability is first shown to be reduced to the probability for a skew constraint graph (a weighted directed graph) to have no positive cycle. Since the computation of the skew adjustability is intractable, the original problem is transformed into "selective ordered coloring problem", which tries to minimize hazardous cycles instead of an exact skew adjustability. An ILP approach of the selective ordered coloring approach is then proposed. Experimental results show not only the effectiveness of our approach, but also how much improvement in the skew adjustability is achieved by equipping one or two extra registers to a datapath circuit.