Dose map and placement co-optimization for improved timing yield and leakage power

Authors:
Kwangok Jeong;Andrew B. Kahng;Chul-Hong Park;Hailong Yao
Affiliations:
Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA;Department of Computer Science and Engineering, University of California at San Diego, La Jolla, CA and Department of Electrical and Computer Engineering, University of California at San Diego, La ...;Semiconductor Research and Development Center, Samsung Electronics, Seoul, Korea;Department of Computer Science and Technology, Tsinghua University, Beijing, China and Department of Computer Science and Engineering, University of California at San Diego, La Jolla, CA
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

In sub-100nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of fine-grain exposure dose control in the step-and-scan tool to achieve both design-time (placement) and manufacturing-time (yield-aware dose mapping) optimizations of timing yield and leakage power. Our placement and dose map co-optimization can improve both timing yield and leakage power of a given design. We formulate the placement-aware dose map optimization as quadratic and quadratic constraint programs which are solved using efficient quadratic program solvers. In this paper, we mainly focus on the placement-aware dose map optimization problem; in the Appendix, we describe a complementary but less impactful dose map-aware placement optimization based on an efficient cell swapping heuristic. Experimental results show noticeable improvements in minimum cycle time without leakage power increase, or in leakage power reduction without degradation of circuit performance.