Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Register placement for low power clock network
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
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In order to achieve multi-GHz operation frequency for VLSI design,clock networks need to be designed in a very elaborated manner andbe able to deliver prescribed useful skews rather than merelyzero-skew. Although traditional zero-skew clock routing methods canbe extended directly to prescribed skews, they tend to result inexcessive wire length as the differences among delay-targets forclock sinks are neglected. In this paper, we propose the maximumdelay-target and minimum merging-cost merging scheme forprescribed-skew clock routing. This scheme is simple yetsurprisingly effective on wirelength reduction. Experimentalresults on benchmark circuits show that our merging scheme yields53%-61% wirelength reduction compared to traditional clock routingmethods.