Formal methods: state of the art and future directions
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Genetic algorithms for VLSI design, layout & test automation
Standard cell and macro cell placement
Genetic algorithms for VLSI design, layout & test automation
Peak power estimation of VLSI circuits: new peak power measures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded System Design: A Unified Hardware/Software Introduction
Embedded System Design: A Unified Hardware/Software Introduction
Automating the Design of SOCs Using Cores
IEEE Design & Test
System-Level Types for Component-Based Design
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Applying Moore's Technology Adoption Life Cycle Model to Quality of EDA Software
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the 19th IEEE international conference on Automated software engineering
Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
GRCA: a hybrid genetic algorithm for circuit ratio-cut partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New advanced library format standard approved
IEEE Design & Test
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Multiprocessor system on chip (MpSoC) platform has set a new innovative trend for the system-on-chip (SoC) design. Demanding Quality of Service (QOS) and performance metrics are leading to the adoption of a new design methodology for MpSoC. These will have to be built around highly scalable and reusable architectures that yield high speed at low cost and high energy efficiency for a variety of demanding applications. Designing such a system, in the presence of such aggressive QOS and Performance requirements, is an NP-complete problem. In this paper, we present the application of genetic algorithms to system level design flow to provide best effort solutions for two specific tasks, viz.., performance tradeoff and task partitioning.