Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETs

  • Authors:

  • Tejasvi Das;Clyde Washburn;P. R. Mukund;Steve Howard;Ken Paradis;Jung-Geau Jang;Jan Kolnik;Jeff Burleson

  • Affiliations:

  • Rochester Institute of Technology;Rochester Institute of Technology;Rochester Institute of Technology;LSI Logic Corporation;LSI Logic Corporation;National Semiconductor Corporation;LSI Logic Corporation;LSI Logic Corporation

  • Venue:
  • VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
  • Year:
  • 2005

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Abstract

In this paper, we present the impact of both process and dimensional scaling on input loss (S_11) prediction of MOSFETýs at GHz frequencies. We study the distributed gate effect, the Non-Quasi Static effect, and report a drop in the resistive component of S_11 for larger fingered devices at high frequencies ( 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S_11 in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logicýs 0.18 µm and 0.11 µm processes, across five different wafers.