Design of half-rate clock and data recovery circuits for optical communication systems
Proceedings of the 38th annual Design Automation Conference
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
A low-power programmable DLL-based clock generator with wide-range antiharmonic lock
IEEE Transactions on Circuits and Systems II: Express Briefs
Digital Integrated Circuits
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For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.