Semi-static threshold-triggered delay elements for low power operation

  • Authors:

  • Louis Hyunsuk Jung;Torsten Lehmann;Gregg Jorgen Suaning;Nigel Hamilton Lovell

  • Affiliations:

  • Graduate School of Biomedical Engineering, The University of New South Wales, Sydney, Australia 2052;School of Electrical Engineering and Telecommunications, The University of New South Wales, Sydney, Australia 2052;Graduate School of Biomedical Engineering, The University of New South Wales, Sydney, Australia 2052;Graduate School of Biomedical Engineering, The University of New South Wales, Sydney, Australia 2052

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2013

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Abstract

Delay elements are widely used in mixed signal integrated circuits in order to meet design-specific timing requirements. Generally delays are generated by lengthening the transition times of the input signal which is subsequently restored. Slow transition times however, results in prolonged short-circuit current duration at the signal restoration stage, not only increasing the overall power consumption of the system but also limiting the usable output delay range. This paper presents a novel CMOS semi-static threshold-triggered delay element architecture that minimizes the short-circuit current over a wide output delay range. The architecture can also incorporate conventional delay elements to improve their performance. The presented delay element is fabricated in a commercial 0.35 μm CMOS technology and the measurement results show significant improvements in output delay range and average power consumption over other conventional delay elements.