Winner-take-all networks of O(N) complexity
Advances in neural information processing systems 1
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Analysis and Design of Integrated Circuits
Analysis and Design of Integrated Circuits
Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
Probability propagation and decoding in analog VLSI
IEEE Transactions on Information Theory
| Hi-index | 0.00 |
In this paper, a novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm (also referred to as max-sum or max-product) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. To demonstrate the functionality of the proposed design, simulation results based on TSMC 0.18mm CMOS technology for a (7,4) Hamming code are also presented.