Iterative decoding in analog CMOS
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A SiGe BiCMOS analog SISO decoder with I/O interface
Analog Integrated Circuits and Signal Processing
A dual-function mixed-signal circuit for LDPC encoding/decoding
Integration, the VLSI Journal
Analog DFT processors for OFDM receivers: circuit mismatch and system performance analysis
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Factorization of joint probability mass functions into parity check interactions
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 3
Analog decoder performance degradation due to BJTs' parasitic elements
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Sparse decoding of low density parity check codes using margin propagation
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Dynamics of analog decoders for different message representation domains
IEEE Transactions on Communications
Scaling of analog LDPC decoders in sub-100nm CMOS processes
Integration, the VLSI Journal
On the dynamics of analog min-sum iterative decoders: an analytical approach
IEEE Transactions on Communications
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The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes