Iterative decoding in analog CMOS
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A dual-function mixed-signal circuit for LDPC encoding/decoding
Integration, the VLSI Journal
Reversible low-density parity-check codes
IEEE Transactions on Information Theory
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An all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s.