The impact of speculative execution on SMT processors

  • Authors:

  • Dongsoo Kang;Chen Liu;Jean-Luc Gaudiot

  • Affiliations:

  • Department of Electrical Engineering, University of Southern California, Los Angeles, CA;Department of Electrical Engineering & Computer Science, University of California, Irvine, Irvine, CA;Department of Electrical Engineering & Computer Science, University of California, Irvine, Irvine, CA

  • Venue:
  • International Journal of Parallel Programming
  • Year:
  • 2008

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Abstract

By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are fetched from multiple threads. However, due to incorrect control speculations, a significant number of these in-flight instructions are discarded from the pipelines of SMT processors (which is a direct consequence of these pipelines getting wider and deeper). Although increasing the accuracy of branch predictors may reduce the number of instructions so discarded from the pipelines, the prediction accuracy cannot be easily scaled up since aggressive branch prediction schemes strongly depend on the particular predictability inherently to the application programs. In this paper, we present an efficient thread scheduling mechanism for SMT processors, called SAFE-T (Speculation-Aware Front-End Throttling): it is easy to implement and allows an SMT processor to selectively perform speculative execution of threads according to the confidence level on branch predictions, hence preventing wrong-path instructions from being fetched. SAFE-T provides an average reduction of 57.9% in the number of discarded instructions and improves the instructions per cycle (IPC) performance by 14.7% on average over the ICOUNT policy across the multi-programmed workloads we simulate.