A comparison of dynamic branch predictors that use two levels of branch history
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Dynamic path-based branch correlation
Proceedings of the 28th annual international symposium on Microarchitecture
Alternative implementations of hybrid branch predictors
Proceedings of the 28th annual international symposium on Microarchitecture
Assigning confidence to conditional branch predictions
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Confidence estimation for speculation control
Proceedings of the 25th annual international symposium on Computer architecture
Improving branch predictors by correlating on data values
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Branch Prediction Using Selective Branch Inversion
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Control-Flow Speculation through Value Prediction for Superscalar Processors
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
The Alpha 21264 Microprocessor Architecture
ICCD '98 Proceedings of the International Conference on Computer Design
Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Dual path instruction processing
ICS '02 Proceedings of the 16th international conference on Supercomputing
Power-Aware Control Speculation through Selective Throttling
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors
IEEE Transactions on Computers
An approach to reduce thread switch frequency for branch
DNCOCO'08 Proceedings of the 7th conference on Data networks, communications, computers
The impact of speculative execution on SMT processors
International Journal of Parallel Programming
Mixed speculative multithreaded execution models
ACM Transactions on Architecture and Code Optimization (TACO)
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Branch prediction reversal has been proved to be an effective alternative approach to dropping misprediction rates by means of adding a Confidence Estimator to a correlating branch predictor. This paper presents a Branch Prediction Reversal Unit (BPRU) especially oriented to enhance correlating branch predictors, such as the gshare and the Alpha 21264 metapredictor. The novelty of this proposal lies on the inclusion of data values in the confidence estimation process. Confidence metrics show that the BPRU can correctly tag 43% of branch mispredictions as low confident predictions, whereas the SBI (a previously proposed estimator) just detects 26%. Using the BPRU to reverse the gshare branch predictions leads to misprediction reductions of 15% for the SPECint2000 (up to 27% for some applications). Furthermore, the BPRU+gshare predictor reduces the misprediction rate of the SBI+gshare by an average factor of 10%. Performance evaluation of the BPRU in a superscalar processor obtains speedups of up to 9%. Similar results are obtained when the BPRU is combined with the Alpha 21264 branch predictor.