Power-efficient clock/data distribution technique for polyphase comb filter in digital receivers

  • Authors:

  • Noha Younis;Mahmoud Ashour;Amin Nassar

  • Affiliations:

  • Microelectronics Design Center, Cairo, Egypt;Microelectronics Design Center, Cairo, Egypt;Electronics and Communications Engineering Department, Cairo Universi!y, Giza, Egypt

  • Venue:
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • Year:
  • 2009

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Abstract

A power-efficient clock/data distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed with respect to the decimation factor. Both proposed and conventional comb filters are implemented using Xilinx Spartan3 low-power field-programmable gate array family. The implementation results show that applying the proposed technique reduces the dynamic power consumption of the second- and third-order polyphase comb filters up to 62.87% and 57.6%, respectively, depending on the decimation factor and the number of quantizer bits. For a particular power consumption, a higher input sampling rate can be utilized by applying the proposed technique. Consequently, the signal-to-noise ratio of a second-order ΣΔ modulator is increased using second- and third-order modified filters by 21.6 and 20.5 dB, respectively, depending on the decimation factor and the number or quantizer bits.