A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits

  • Authors:

  • Fei Yuan

  • Affiliations:

  • Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada M5B 2K3. fyuan@ee.ryerson.ca

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2004

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Abstract

This paper presents a detailed analysis of the clock-skew induced hazards in pipelined NORA dynamic circuits. We show that both NP-pipelined and PN-pipelined NORA dynamic circuits are sensitive to clock skew. In addition, by defining positive and negative clock skews, these circuits exhibit distinct clock skew sensitivities. These findings differ from the results given in the original paper in which NORA dynamic circuits were introduced (N. Goncalves and H. Den Man, J. Solid-State Circuits, vol. 18, pp. 261–266, 1983) and those in most text books on this subject. In assessment of these observations, two full adders implemented using PN- and NP-configurations are designed using a 0.35 micron CMOS technology. They are analyzed using Spectre from Cadence Design Systems in the presence of clock skews. Simulation results are presented.