A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder

  • Authors:

  • Peter Celinski;Sorin D. Cotofana;Derek Abbott

  • Affiliations:

  • Centre for High Performance Integrated Technologies & Systems (CHiPTec), Australia and Computer Engineering Group, Electrical Engineering Department, Delft University of Technology, CD Delft, The ...;Computer Engineering Group, Electrical Engineering Department, Delft University of Technology, CD Delft, The Netherlands 2628;Centre for Biomedical Engineering, The Department of Electrical and Electronic Engineering, The University of Adelaide, SA, Australia 5005

  • Venue:
  • IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
  • Year:
  • 2009

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Abstract

A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 μm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.