Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
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This paper presents the design and analysis of Low Powered DNA sequence alignment accelerator using ASIC design flow. The objective of this paper is to design and analyze DNA sequence alignment accelerator using clock cycle reduction and frequency scaling technique, which the power consumption can be optimize. The scope of this paper focuses on the minimization of power consumption for an ASIC DNA sequence alignment accelerator on the matrix filling module of the Smith-Waterman algorithm. Smith-Waterman algorithm is a sensitive algorithm used for procedure of DNA sequence alignment in computational molecular biology. As the number of DNA sequence database increases exponentially, it affects the performance of Smith-Waterman algorithm in general purpose computer. Therefore several techniques have been developed to optimize the performance of the algorithm by exploiting parallelism in the design. The low-powered part of the design focuses on the frequency scaling where it produces the minimal value of dynamic power. The design are described using Verilog HDL coding and compiled using Synopsys Tools. From the data obtained using Synopsys tools, the data is then manipulated to get the optimum combination of parameters to produce the most energy efficient IC. The design produces an ASIC that can work at 25ns-50ns clock period where it is in the high energy efficiency region. This range of frequencies produce dynamic power ranging from 224µW-89µW.